If you are a designer of a chip that uses several serial interface transceivers with multiple protocols, you know that the serial verification can be a challenge. Let's say you're designing an ASIC with a 10 Gig Ethernet transceiver, a Serial RapidIO transceiver, and a CPRI transceiver. One of the biggest challenges is to verify data integrity of the serial links as it passed from one protocol domain to the next. In the path there may be switches, bridges, and other components.
DSPs, ASICs, and FPGAs can support multiple transceivers with multiple protocols. As bandwidth requirements increase, serial busses are expected to proliferate throughout designs.
Many test manufacturers today have test equipment that can handle ONE protocol at a time. Some have the capability to handle two, but reporting the traces in a time correlated fashion, so the engineer can understand where problems may lie, is a very big challenge for most test equipment manufacturers.
Enter InvestigatorTM from Absolute Analysis. The InvestigatorTM platform can handle over 15 different standard protocols, and also custom protocols, all on the same hardware. It has the capability to report traces from serial test results in a time correlated fashion, so the engineer knows how data is flowing in each of the domains, and where exactly the problems lie.
In post silicon verification in particular, mixed protocol verification is critical to characterizing performance and behavior. This is important because future users of the chip will need this characterization data to be able to use the chip within their boards and embedded systems. If certain behavior like error recovery is not characterized, the vendor faces support headaches as users may encounter problems with interoperability.
